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single - /dual - supply, high voltage isolated igbt gate driver with miller clamp rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. te l: 781.329.4700 ? 2015 analog devices, inc. all rights reserved. technical support www.analog.com features 4 a peak drive output capability outp ut power device resistance : <1 ? desaturation protection isolated desaturation fault report ing soft shutdown on faul t miller clamp output with gate sense input isolated fault and ready functi ons low propagation delay : 55 ns typical minimum p ulse width : 50 ns operating temperature range : ? 40 c to + 125 c output voltage r ange to 30 v input v oltage range from 2.3 v to 6 v output and input undervoltage lock out ( uvlo ) c reepage distance : 7.8 mm minimum 100 kv/s common-m ode t ransient immunity (cmti) 20 year lifetim e for 600 v rms or 1092 v dc working vo ltage safety and regulatory approvals (pending) 5 kv ac for 1 minute per ul 1577 csa c omp onent acceptance notice 5a din v vde v 0 884 - 10 (vde v 0884 - 10):2006 -12 v iorm = 849 v peak (reinforced/basic) applications mosfet/i gbt gate drivers pv i nverters mot or drives power supplies general description the ADUM4135 is a single - channel gate driver specifically optimized for driving insulated gate bipolar transistor s (igbts). analog devices, inc. , i coupler? technology provides isolation between the input signal and the output gate drive. the ADUM4135 includes a m iller clamp to provide robust igbt turn - off with a single - rail supply when the gate voltage drops below 2 v. operation with unipolar or bipolar secondary supplies is possible , with or wit hout the m iller clamp operation. the analog devices chip scale transformer s also provide isolated communication of control information between the high voltage and low voltage domains of the chip . information on the status of the chip can be r ead back from dedicated outputs. control of resetting the device after a fault on the secondary is performed on the primary side of the device. integrated onto the ADUM4135 is a desaturation d etection circuit that provides protection against high voltage short - circuit igbt operation. the desaturation protection contains noise reducing features such as a 300 ns masking time after a switching event to mask voltage spikes due to initial turn - on. a n internal 500 a current source allows low device count, while the internal blanking switch allows the addition of an external current source if more noise immunity is needed. the secondary uvlo is set to 11 v with common igbt threshold levels taken into consideration . functional block dia gram 13082-001 master logic primary v ss1 1 1 2 2 2 2 2 1 1 1 v ss2 2v v dd2 v out_on v out_off gnd 2 desat v dd1 v ss1 v i + v i ? ready gate_sense fault reset uvlo 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 master logic secondary tsd encode decode decode encode clamp logic uvlo v ss2 9 9v ADUM4135 notes 1. grounds on primary and secondary side are isolated from each other. figure 1 .
ADUM4135 data sheet rev. a | page 2 of 17 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 electrical characteristics ............................................................. 3 package characteristics ............................................................... 5 regulatory information ............................................................... 5 insulation and safety related specifications ............................ 5 din v vde v 0884 - 10 (vde v 0884 - 10) insulation characteristics .............................................................................. 6 recommended operating conditions ...................................... 6 absolute maximum ratings ............................................................ 7 esd caution ...................................................................................7 pin configuration and function descriptions ..............................8 typical performanace characteristics ............................................9 applications information .............................................................. 12 pcb layout ................................................................................. 12 propagation delay related parameters ................................... 12 protection features .................................................................... 12 power dissipation ....................................................................... 14 dc correctness and magnetic field immunity ........................... 15 insulation l ifetime ..................................................................... 15 typical application .................................................................... 16 outline dimensions ....................................................................... 17 ordering g uide .......................................................................... 17 revision history 9 /15 rev. 0 to rev. a changes to features section ............................................................ 1 changed t a to t j .............................................................................. 3 added common - mode transient immunity (cmti) parameter, table 1 ............................................................................. 4 changes to table 3 and table 4 ....................................................... 5 changes to table 6 ............................................................................ 6 changes to table 7 ............................................................................ 7 cha n ges to figure 16 caption and figure 17 caption .............. 11 chan g es to fault reporting section ............................................. 12 change to figure 28 ....................................................................... 16 7/ 15 revisio n 0: initial versi on
data sheet ADUM4135 rev. a | page 3 of 17 specifications electrical character istics low - si de voltages referenced to v ss1 . high - side voltages referenced to gnd 2 , 2. 3 v v dd1 6 v , 12 v v dd2 30 v , and t j = ? 40c to +125c . all m inimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. all typical specifications are at t j = 25 c, v dd1 = 5.0 v, and v dd2 = 15 v . table 1. parameter symbol min typ max unit test conditions/comments dc specifications high - side power supply input voltage v dd2 v dd2 12 30 v v dd2 ? v ss2 30 v v ss2 v ss2 ? 15 0 v input current, quiescent ready high v dd2 i dd2 (q) 3.62 4.37 ma v ss2 i ss2 ( q) 4.82 6.21 ma logic supply v dd1 input voltage v dd1 2.3 6 v input current i dd1 output low 1.78 2.17 ma output signal low output high 4.78 5.89 ma output signal high logic inputs ( v i +, v i ? , reset ) input current ( v i +, v i ? o nly) i i ? 1 + 0.01 + 1 a logic high input voltage v ih 0.7 v dd1 v 2.3 v v dd1 ? v ss1 5 v 3.5 v v dd1 ? v ss1 > 5 v logic low input voltage v il 0.29 v dd1 v 2.3 v v dd1 ? v ss1 5 v 1.5 v v dd1 ? v ss1 > 5 v reset internal pull - down r reset _pd 300 k ? uvlo v dd1 positive going threshold v vdd1 uv+ 2.23 2.3 v v dd1 negative going threshold v vdd1 uv ? 2.0 2.135 v v dd1 hysteresis v vdd1 uvh 0.095 v v dd2 positive going threshold v vdd2 uv+ 11. 5 12.0 v v dd2 negative going threshold v vdd2 uv ? 10.4 11.1 v v dd2 hysteresis v vdd2 uvh 0.4 v fault pull -d own fet resistance r fault _pd_fet 11 50 ? tested at 5 ma ready pull -d own fet resistance r rdy_pd_ fet 11 50 ? tested at 5 ma desaturation (desat ) desaturation detect comparator voltage v desat, th 8.73 9.2 9.61 v internal current source i desat_src 481 537 593 a thermal shutdown tsd positive edge t tsd_ pos 155 c tsd hysteresis t tsd_ hyst 20 c miller clamp voltage threshold v clp_th 1.75 2 2.25 v referenced to v ss2 internal nmos gate resistance r dson_n 315 625 m ? tested at 250 ma 318 625 m ? tested at 1 a internal pmos gate resistance r dson_p 471 975 m ? tested at 250 ma 479 975 m ? tested at 1 a
ADUM4135 data sheet rev. a | page 4 of 17 parameter symbol min typ max unit test conditions/comments soft shutdown nmos r dson_fault 10.2 22 tested at 250 ma internal miller clamp resistance r dson_miller 1.1 2.75 tested at 100 ma peak current 4.61 a v dd2 = 12 v, 2 gate resistance switching specifications pulse width 1 pw 50 ns c l = 2 nf, v dd2 = 15 v, r gon 2 = r goff 2 = 3.9 reset debounce t deb_ reset 500 615 700 ns propagation delay 3 t dhl , t dlh 40 55 66 ns c l = 2 nf, v dd2 = 15 v, r gon 2 = r goff 2 = 3.9 propagation delay skew 4 t psk 15 ns c l = 2 nf, r gon 2 = r goff 2 = 3.9 , v dd1 = 5 v to 6 v output rise/fall time (10% to 90%) t r /t f 11 16 22.9 ns c l = 2 nf, v dd2 = 15 v, r gon 2 = r goff 2 = 3.9 blanking capacitor discharge switch masking t desat_delay 213 312 529 ns time to report desaturation fault to fault pin t report 0.5 2 s common-mode transient immunity (cmti) |cm| 100 kv/s v cm = 1000 v static cmti 5 dynamic cmti 6 1 the minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed. 2 see the power dissipation section. 3 t dlh propagation delay is measured from the time of the input rising logic high threshold, v ih , to the output rising 10% threshold of the v outx signal. t dhl propagation delay is measured from the input falling logic low threshold, v il , to the output falling 90% threshold of the v outx signal. see figure 20 for waveforms of propagation delay parameters. 4 t psk is the magnitude of the worst case difference in t dlh and/or t dhl that is measured between units at the same operating temperature , supply voltages, and output load within the recommended operating conditions. see figure 20 for waveforms of propagation delay parameters. 5 static common-mode transient immunity (cmti) is defined as the largest dv/dt between v ss1 and v ss2 , with inputs held either high or low, such that the output voltage remains either above 0.8 v dd2 for output high or 0.8 v for output low. operation with transients above recommended levels can cause momentary data upsets. 6 dynamic common-mode transient immunity (cmti) is defined as the largest dv/dt between v ss1 and v ss2 with the switching edge coincident with the transient test pulse. operation with transients above recommended levels can cause momentary data upsets.
data sheet ADUM4135 rev. a | page 5 of 17 package characteristics table 2. parameter symbol min typ max unit test conditions/comments resistance (input side to high - side output) 1 r i-o 10 12 ? capacitance (input side to high - side output) 1 c i-o 2.0 pf input capacitance c i 4.0 pf junction to ambient thermal resistance ja 75.4 c/w 4- layer printed circuit board ( pcb ) junction to case thermal resistance jc 35.4 c/w 4- layer pcb 1 the device is considered a two - terminal device: pin 1 through pin 8 are shorted together, and pin 9 through pin 16 are shorted together. regulatory informati on the ADUM4135 is pending approval by the organizations listed in table 3 . table 3. ul (pending) csa (pending) vde (pending) recognized under ul 1577 component recognition program 1 approved under csa component acceptance notice 5a certified according to vde0884-10 2 single protection, 50 00 v rms isolation voltage basic insulation per csa 60950-1- 07+a1+a2 and iec 60950-1, second edition , +a1+a2, 780 v rms (1103 v peak) maximum working voltage r einforced insulation, 849 v peak basic insulation, 849 v peak reinforced insulation per csa 60 950-1- 07+a1+a2 and iec 60950-1, second edition , +a1+a2, 390 v rms (551 v peak) maximum working voltage file e214100 file 205078 file 2471900 -4880-0001 1 in accordance with ul 1577, each ADUM4135 is proof tested by app lying an insulation test voltage 6000 v rms for 1 second (current leakage detection limit = 10 a). 2 in accordance with din v vde v 0884 - 10, each ADUM4135 is proof tested by applying an insulation test voltage 1590 v peak for 1 second (partial discharge detection limit = 5 pc). an asterisk (*) marking branded on the component designates din v vde v 0884 - 10 approval. insulation and safet y related specifications table 4. parameter symbol value unit test conditions/comments rated dielectric insulation voltage 5000 v rms 1 minute duration minimum external air gap (clearance) l(i01) 7.8 min mm measured from input terminals to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) 7.8 min mm measured from input terminals to output terminals, shortest distance path along body minimum internal gap (internal clearance) 0.026 min mm insulation distance through insulation tracking resistance (comparative tracking index) cti >400 v din iec 112/vde 0303 part 1 isolation group ii material group (din vde 0110, 1/89, table 1)
ADUM4135 data sheet rev. a | page 6 of 17 din v vde v 0884 - 10 (vde v 0884- 10) insulation characteristics this isolator is suitable for reinforced isolation only within the safety limit data. maintenance of the safety data is ensured by protective circuits. the asterisk (*) marking on the package denotes din v vde v 0884 - 10 approval for a 560 v peak working voltage. table 5 . vde characteristics description test conditions /comments symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 150 v rms i to iv for rated mains voltage 300 v rms i to iii for rated mains voltage 400 v rms i to ii climatic classification 40/105/21 pollution degree per din vde 0110, table 1 2 maximum working insulation voltage v iorm 849 v peak input to output test voltage, method b1 v iorm 1.875 = v pd (m) , 100% production test, t ini = t m = 1 sec, partial discharge < 5 pc v pd (m) 1592 v peak input to output test voltage, method a after environmental tests subgroup 1 v iorm 1.5 = v pd (m) , t ini = 60 sec, t m = 10 sec, partial discharge < 5 pc v pd (m) 1274 v peak after input and/or safety test subgroup 2 and subgroup 3 v iorm 1.2 = v pd (m) , t ini = 60 sec, t m = 10 sec, partial discharge < 5 pc v pd (m) 1019 v peak highest allowable overvoltage v iotm 8000 v peak surge isolation voltage v peak = 12.8 kv, 1.2 s rise time, 50 s, 50% fall time v iosm 8000 v peak safety limiting values maximum value allowed in the event of a failure (see figure 2 ) maximum junction temperature t s 150 c safety total dissipated power p s 2.77 w insulation resistance at t s v io = 500 v r s >10 9 ? 13082-002 safe operating p vdd1 , p vdd1 , p vdd1 power (w) ambient temperature (c) 0 50 3.0 2.5 2.0 1.5 1.0 0.5 0 100 150 200 figure 2 . ADUM4135 thermal derating curve, dependence of safety limiting values on case temperature, per din v vde v 0884 - 10 recommended operatin g conditions table 6. parameter value operating temperature range (t a ) ? 40c to +1 25c supply voltages v dd1 1 2.3 v to 6 v v dd2 2 12 v to 30 v v dd2 ? v ss2 2 12 v to 30 v v ss2 2 ?15 v to 0 v input signal rise/fall time 1 ms static common - mode transient immunity 3 ?100 kv/s to +100 kv/s dynamic common - mode transient immunity 4 ?100 kv/s to +100 kv/s 1 referenced to v ss1 . 2 re ferenced to gnd 2 . 3 static common - mode transient immunity is defined as the largest dv/dt between v ss1 and v ss2 , with inputs held either high or low , such that the output voltage remains either above 0.8 v dd2 for o utput high or 0.8 v for output low. operation with transients above recommended levels can cause momentary data upsets. 4 dynamic common - mode transient immunity is defined as the largest dv/dt between v ss1 and v ss2 with the switching edge coincident with the transient test pulse. operation with transients above recommended levels can cause momentary data upsets.
data sheet ADUM4135 rev. a | page 7 of 17 absolute maximum rat ings table 7. parameter rating storage temperature range (t st ) ?55 c to +150c ambient operating temperature range (t a ) ?40c to +1 2 5c supply voltages v dd1 1 ?0.3 v to +6.5 v v dd2 2 ? 0.3 v to +40 v v ss2 2 ? 20 v to +0.3 v v dd2 ? v ss2 2 35 v input voltages v i +, v i ?, reset ?0.3 v to +6.5 v v desat ? 0.3 v to v dd2 + 0.3 v v gate_ sense ? 0.3 v to v dd2 + 0.3 v v out_on ? 0.3 v to v dd2 + 0.3 v v out_off ?0.3 v to v dd2 + 0.3 v v out_on , v out_off c urrent for 1.5 s at 15 khz 6 a common - mode transients (|cm|) ?1 50 kv/s to +1 5 0 kv/s 1 referenced to v ss1 . 2 referenced to gnd 2 . stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond th e maximum operating conditions for extended periods may affect product reliability. table 8. maximum continuous working voltage 1 parameter value constraint 60 hz ac voltage 600 v rms 20 year lifetime at 0.1% failure rate, zero average voltage dc voltage 1092 v peak limited by the creepage of the package, pollution degree 2, material group ii 2, 3 1 see the insulation lifetime section for details. 2 other pollution degree and material group requirements yield a different limit. 3 some system level standards allow components to use the printed wiring board (pwb) cre epage values. the supported dc voltage may be higher for those standards. esd caution table 9 . truth table (positive logic) 1 v i + input v i ? input reset pin ready pin fau lt pin v dd1 state v dd2 state v gate 2 l l h h h powered powered l l h h h h powered powered l h l h h h powered powered h h h h h h powered powered l x x h l unknown powered powered l x x h unknown l powered powered l l l h l unknown unpowered powered l x x l 3 unknown h 3 powered powered l x x x l unknown powered unpowered unknown 1 x is dont care, l is low, and h is high. 2 v gate is the voltage of the gate being driven. 3 time dependent value. see the absolute maximum ratings section for details on timing.
ADUM4135 data sheet rev. a | page 8 of 17 pin configuration an d function descripti ons 13082-003 1 2 3 4 ADUM4135 top view (not to scale) 5 6 16 15 14 13 12 11 7 8 9 10 v ss1 v ss2 v ss1 v ss2 v dd2 desat gnd 2 v dd1 ready fault v i + v i ? v out_off v out_on gate_sense reset figure 3 . pin configuration table 10 . pin function descriptions pin no. mnemonic description 1, 8 v ss1 ground reference for primary si de. 2 v i + positive l ogic cmos input drive sig nal . 3 v i ? negative l ogic cmos input drive sign al . 4 ready open - drain logic o utput. connect this pin to a pull - up resistor to read the signal. a high state on this pin indicates that the device is functional and ready to operate as a gate driver. the p resence of ready low precludes the gate drive output from goin g high. 5 fault open - drain logic outp ut. connect this pin to a pull - up resistor to read the signal. a l ow state on this pin indicates when a de saturation fault has occurred. the p resence of a fault condition precludes the gate drive output from going high. 6 reset cmos i nput. when a fault exists, bring this pin low to clear the fault. 7 v dd1 input supply voltage on primary sid e, 2.3 v to 5.5 v r eferenced to v ss1 . 9, 16 v ss2 negative s upply for secondary s ide, ? 15 v to 0 v r eferenced to gnd 2 . 10 d esat detection of desaturation co ndition. connect this pin to an external current source or a pull - up resistor. this pin c an allow ntc temperature detection or other fault conditions. a fault on this pin asserts a fault on the fault pin on the primary side. until the fault is cleared on the primary side, the g ate drive is suspended. during a fault condition, a smaller turn - off fet slowly bring s the gate voltage down. 11 gnd 2 ground reference for secondary s ide. connect this pin to the e mitter of the igbt or the s ource of the mosfet being driven. 12 v out_off gate drive output current pat h for off sign al. 13 v dd2 secondary side input supply vol tage, 12 v to 30 v r eferenced to gnd 2 . 14 v out_on gate drive output current pa th for on s ignal. 15 g ate_sense gate voltage sense input and miller clamp output . connect this pin to the gate of the power device being driven. this pin sense s the gate voltage for the purpose of miller clamping . when the miller clamp is not used, t ie gate_sense to vss2.
data sheet ADUM4135 rev. a | page 9 of 17 typical performanace characteristics ch1 520mv 2 1 13082-004 ch2 5.0v ch1 2.0v m 100ns 10.0gs/s 20.0ps/pt a b w b w ch1 = v i + (2v/div) ch2 = v gate (2v/div) figure 4 . typical input to output waveform, 2 nf load, 5.1 ? series gate resistor, v dd1 = + 5 v, v dd2 = + 15 v, v ss2 = ? 5 v 2 1 13082-005 ch1 520mv ch2 5.0v ch1 2.0v m 100ns 10.0gs/s 20.0ps/pt a b w b w ch1 = v i + (2v/div) ch2 = v gate (5v/div) figure 5 . typical input to output waveform, 2 nf load, 5.1 series gate resistor, v dd1 = 5 v, v dd2 = 15 v, v ss2 = 0 v 2 1 13082-006 ch1 960mv ch2 5.0v ch1 2.0v m 100ns 10.0gs/s 20.0ps/pt a b w b w ch1 = v i + (2v/div) ch2 = v gate (5v/div) figure 6 . typical input to output waveform, 2 nf load, 3.9 series gate resistor, v dd1 = +5 v, v dd2 = +15 v, v ss2 = 5 v 2 1 13082-007 ch1 520mv ch2 5.0v ch1 2.0v m 100ns 10.0gs/s 20.0ps/pt a b w b w ch1 = v i + (2v/div) ch2 = v gate (5v/div) figure 7 . typical input to output waveform, 2 nf load, 3.9 series gate resistor, v dd1 = 5 v, v dd2 = 15 v, v ss2 = 0 v 13082-008 frequency (hz) 0 0.5 200k 400k 600k 800k 1m 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 i dd1 (ma) v dd1 = 2.3v v dd1 = 5.0v v dd1 = 3.3v figure 8 . typical i dd1 current vs. frequency, duty = 50%, v i + = v dd1 13082-009 frequency (hz) 200k 400k 600k 800k 1m 0 i dd2 (ma) 0 10 20 30 40 50 60 v dd2 = 20v v dd2 = 15v v dd2 = 12v figure 9 . typical i dd2 current vs. frequency, duty = 50%, 2 nf l oad, v ss2 = 0 v
ADUM4135 data sheet rev. a | page 10 of 17 2 3 1 13082-010 ch3 6.0v ch2 5.0v ch1 5.0v m 10.0s 1.0gs/s 1.0ns/pt a b w ch3 10.0v b w b w ch3 = v dd2 (10v/div) ch2 = v gate (5v/div) ch1 = v i + (5v/div) figure 10 . typical v dd2 s tartup to output val id 13082 - 011 pr o pa g a t io n d el a y (n s) v dd 2 (v) 1 0 1 2 1 7 2 2 2 7 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 t d l h t dhl figure 11 . typical propagation delay vs. output supply voltage (v dd2 ) for v dd2 = 15 v and v dd1 = 5 v 13082-012 rise/fall time (ns) v dd2 (v) 12 17 22 27 5 0 10 15 20 25 30 t dlh t dhl figure 12 . typical rise /fall time vs. v dd2 , v dd2 ? v ss2 = 12 v, v dd1 = 5 v, 2 nf load, r g = 3.9 13082-013 propagation delay (ns) input supply voltage (v) 0 10 20 30 40 50 60 70 80 2.3 3.3 4.3 5.3 t dlh t dhl figure 13 . typical propagation delay vs. input supply voltage, v dd2 v ss2 = 12 v 13082-014 propagation delay (ns) ambient temperature (c) 0 10 20 30 40 50 60 70 80 ?40 10 60 110 t dlh t dhl figure 14 . typical propagation delay vs. ambient temperature, v dd2 = 5 v, v dd2 ? v ss2 = 12 v 2 3 4 1 13082-015 ch1 3.1v ch2 10.0v ch1 5.0v m 200ns 5.0gs/s 200ps/pt a b w b w ch4 5.0v ch3 5.0v b w b w ch1 = v i + (5v/div) ch2 = v gate (10v/div) ch4 = desat (5v/div) ch3 = fault (5v/div) figure 15 . example desaturation event and reporting
data sheet ADUM4135 rev. a | page 11 of 17 13082-016 r dson (m) temperature (c) 0 100 200 300 400 500 600 700 800 ?40 ?20 0 20 40 60 80 100 120 source resistance sink resistance figure 16 . typical output resistance ( r dson ) vs. temperature, v dd2 = 15 v, 250 ma t est 13082-017 r dson (m) temperature (c) 0 100 200 300 400 500 600 700 800 ?40 ?20 0 20 40 60 80 100 120 source resistance sink resistance figure 17 . typical output resistance ( r dson ) vs. temperature, v dd2 = 15 v, 1 a t est 2 3 1 13082-018 ch3 6.0v ch2 5.0v ch1 5.0v m 10.0s 1.0gs/s 1.0ns/pt a b w ch3 10.0v b w b w ch1 = v i + (5v/div) ch2 = v gate (5v/div) ch3 = reset (5v/div) figure 18 . example reset to o utput valid 13082-019 peak output current (a) output supply voltage (v) 0 1 2 3 4 5 6 7 8 9 12 14.5 17 19.5 22 24.5 peak source i out peak sink i out figure 19 . typical peak output curr ent vs. output supply voltage, 2 series resistance ( i out is the current going i nto/ o ut o f the device gate )
ADUM4135 data sheet rev. a | page 12 of 17 application s information pcb layout the ADUM4135 igbt gate driver requires no external interface circuitry for the logic interfaces. power supply bypassing is required at the inpu t and output supply pins. use a small ceramic capacitor with a value between 0.01 f and 0.1 f to provide a good high frequency bypass. on the output power supply pin, v dd2 , it is recommended also to add a 10 f capacitor to provide the charge required to drive the gate capacitance at the ADUM4135 outputs . on the output supply pin, avoid the use of vias on the bypass capacitor or employ multiple vias to reduce the inductance in the bypassing. the total lead length between both en ds of the smaller capacitor and the input or output power supply pin must not exceed 5 mm. propagation delay related parameters propagation delay describes the time it takes a logic signal to propagate through a component. the propagation del ay to a low ou tput can differ from the propagation delay to a high output. the ADUM4135 specifies t dlh as the time between the rising input high logic threshold ( v ih ) to the output rising 10% threshold (see figure 20 ) . likewise, the falling propagation delay ( t dhl ) is defined as the time between the input falling logic low threshold ( v il ) and the output falling 90% threshold. the rise and fall times are dependent on the loading conditions and are not included in the propagation delay, which is the industry standard for gate drivers. output input 90% 10% v ih v il t dlh t r t f t dhl 13082-020 figure 20 . propagation delay parameters propa gation delay skew refers to the maximum amount that the propagation delay differs between multiple ADUM4135 components operating under the same temperature, input voltage, and load conditions. protection features f ault reporting the ADUM4135 provide s protection for faults that may occur during the operation of an igbt. the primary fault condition is desaturation. if saturation is d etected, the ADUM4135 shuts down the gate drive and asserts fault low. the output remains disabled until reset is brought low for more than 500 ns , and is then brought high . fault resets to high on the falling edge of reset . while reset remains held low , the output remains disabled. the reset pin has an internal , 300 k ? pull - down resistor. desaturation detection occasionally, component failures or faults occur with the circuitry connected to the igbt connected to the ADUM4135 . examples include shorts in the inductor/motor windings or shorts to power/ground buses. the resulting excess in current flow causes the igbt to come out of saturation. to detect this condition and to reduce the likelihood of damage to the fet, a threshold circuit is used on the ADUM4135 . if the desat pin exceeds the desaturation threshold ( v desat, th ) of 9 v while the high - side driver is on, the ADUM4135 enter s the failure state and turn s the igbt off . at this time, the fault pin is brought low . an internal current source of 500 a is provided, as well as the option to boost the charging current using external current sources or pull - up resistor s. the ADUM4135 has a built - in blanking time to prevent false triggering while the igbt first turn s on. the time between desat uration detection and reporting a desaturation fault to the fault pin is less than 2 s ( t report ) . bring reset low to clear t he fault . there is a 5 00 ns debounce ( t deb_ reset ) on the reset pin . the time , t desat_delay , shown in figure 21, provides a 3 00 ns masking time that keeps the internal switch that grounds the blanking capacitor tied low for the initial portion of the ig bt on time. 13082-021 v desat v dd2 v f 9v fault v ce 9v < 200ns v gate desat switch on off off v i + desat event on on ~2s recommended t report < 2s t desat_delay = 300ns figure 21 . desaturation detection timing diagram
data sheet ADUM4135 rev. a | page 13 of 17 for the following design example, see the schematic shown in figure 28 along with the waveforms in figure 21 . under normal operation, during igbt off times, the voltage across the igbt, v ce , rises to the rail voltage supplied to the system. in this case, the blocking diode shuts off, protecting the ADUM4135 from high voltages. during the off time s, the internal desaturation switch is on, accepting the current going through the r blank resistor, which allows the c blank capacitor to remain at a low voltage. for the first 3 00 ns of the igbt on time, the desat switch remains on, clamping the desat pin voltage low. after the 3 00 ns delay time, the desat pin is released, and the desat pin is allowed to rise towards v dd2 either by the internal current source on the desat pin, or additionally with an optional externa l pull - up , r blank , to increase the c urrent drive if it is not clamped by the collector or drain of the switch being driven . v rdesat is chosen to dampen the current at this time, usually selected around 100 to 2 k ? . select t he blocking diode to block above the high rail voltage on the collector of the igbt and to be a fast recovery diode. in the case of a desaturation event, v ce rise s above the 9 v threshol d in the desaturation detection circuit. if no r blank resistor is used to increase the blanking current, the voltage on the blanking capacitor , c blank , rise s at a rate of 500 a (typical) divided by the c blank capacitance. depending on the igb t specifications, a bla nking time of approximately 2 s is a typical design choice . when the desat pin rises above the 9 v threshold, a fault register s , and within 200 ns, the gate output drive s low. the output is brought low using the n - fet f ault mosfet , which is approximately 50 times more resistive than the internal gate driver n - fet , to perform a soft shutdown to reduce the chance of an over v oltage spike on the igbt during an abrupt turn - off event. within 2 s, the fault is communicated back to the primary side fault pin. to clear the fault, a r eset is required. mill er clamp the ADUM4135 has an integrated miller clamp to reduce voltage spikes on the igbt gate caused by the miller capacitance during shut - off of the igbt. when the input gate signal calls fo r the igbt to turn off (driven low), the miller clamp mosfet is initially off. when the voltage on the gate_sense pin crosses the 2 v internal voltage reference , as ref e renced to v ss2 , the internal miller clamp latches on for the remainder of the off time of the ig bt, creating a second low impedance current path for the gate current to follow. the m iller clamp switch remain s on until the input drive signal changes from low to high . an example waveform of the timings is shown in f igure 22. on off off v i + v i ? v gate_sense v dd2 v ss2 2v latch on miller clamp switch latch off 13082-022 figure 22 . miller clamp example thermal shutdown if the internal temperature of the ADUM4135 exceeds 15 5 c (typical), the device enter s thermal shutdown (tsd) . during the thermal shutdown time , the ready pin is brought low on the primary side, and the gate drive is disable d. when tsd occur s , the device does not leave tsd until the interna l temperature drop s below 125 c (typical), at which time the ready pin return s to high, and the device exit s shutdown. undervo ltage l ockout (uvlo) faults uvlo faults occur when the supply voltages are below the specified uvlo threshold values. during a uvlo event on either the primary side or secondary side, the ready pin goes low, and the gate drive is disabled. when the uvlo condition is removed , the device resumes operation , and the ready pin goes high . ready pin the open - drain ready pin is an output that confirms communication between the primary to secondary sides is active. the ready pin remain s high when there are no uvlo or tsd events present. when the ready pin is low, the igbt gate is driven low . table 11. ready pin logic table vl td r eady pin utput no no high yes no low no yes low yes yes low
ADUM4135 data sheet rev. a | page 14 of 17 fault pin the open - drain fault pin is an output to communicate that a desaturation f ault has occurred. when the fault pin is low, the igbt gate is driven low. if a desaturation event occurs, the reset pin must be driven low for at least 500 ns, then high to return operation to the igbt gate drive. reset pin the reset pin has an internal 300 k ? (typical) pull - down resistor. the reset pin accepts cmos level logic. when the reset pin is held low, after a 500 ns debounce time, any faults on the fault pin are cleared. while the reset pin is held low, the switch on v out_off i s closed, bringing the gate voltage of the igbt low. when reset is brought high, and no fault exists, the device resumes operation. 13082-023 reset fault <500ns 500ns figure 23 . reset timing v i + and v i ? operation the ADUM4135 has two drive inputs, v i + and v i ? , to control the igbt gate drive signal s, v out_on and v out_off . both the v i + and v i ? inputs u s e cmos logic level inputs. the input logic of the v i + and v i ? pins can be controlled by either asserting the v i + pin high or the v i ? pin low. with the v i ? pin low, the v i + pin accepts positive logic. if v i + is held high, the v i ? pin accepts negative logic. if a fault is asserted, transmission is blocked until the fault is cleared by the reset pin. 13082-024 v i + fault v i ? v out_on v out_off 2 figure 24 . v i + and v i ? block diagra m the minimum pulse width, pw, is the minimum period in which the timing specifications are guaranteed. gate resistance selection the ADUM4135 provides two output nodes for the driving of an igbt. the benefit of this approach is that the user can select two different series resistances for the turn - on and turn - off of the igbt. it is generally desired to have the turn - off occur faster than the tu rn - on. to s elect the series resistance , decid e what the maximum allowed peak current is for the igbt. knowing the voltage swing on the gate, as well as the internal resistance of the gate driver, an external resistor can be chosen. i peak = ( v dd2 ? v ss2 )/( r dson_n + r goff ) for example, if the turn - off peak current is 4 a, with a (v dd2 ? v ss2 ) of 18 v, r goff = ((v dd2 ? v ss2 ) ? i peak r dson_n )/ i peak r goff = (18 v ? 4 a 0.6 ? )/4 a = 3.9 ? after r goff is selected, a slightly larger r gon can be selected to arrive at a slower turn - on time. power dissipation during the driving of an igbt gate, the driver must dissipate power. this power is not insignificant and can lead to tsd if considerations are not made. the gate of an igbt can be rough ly simulated as a capacitive load. due to m iller capacitance and other nonlinearities, it is common practice to take the stated input capacitance, c iss , of a given igbt, and multiply it by a factor of 5 to arrive at a conservative estimate to approximate t he load being driven. with this value, the estimated total power dissipation in the system due to switching action is given by p diss = c est ( v dd2 ? v ss2 ) 2 f s w here : c est = c iss 5 . f s is the switching frequency of the ig bt. this power dissipation is shared between the internal on resistances of the internal gate driver switches and the external gate resistances , r gon and r goff . the ratio of the internal gate resistances to the total series resistance allows the calculation of losses seen within the ADUM4135 chip. p diss _ADUM4135 = p diss 0.5( r dson_p /( r gon + r dson_p ) + r dson_n /( r goff + r dson_n )) ta k ing t h e power dissipation found inside the chip and multiplying it by the ja gives the rise above ambient temperature that the ADUM4135 experience s. t ADUM4135 = ja p diss _ADUM4135 + t amb for the device to remain within specification , t ADUM4135 must not exceed 125 c. if t ADUM4135 exceeds 15 5 c ( t ypical) , the device enter s thermal shutdown .
data sheet ADUM4135 rev. a | page 15 of 17 dc correctness and m agnetic field immuni ty the ADUM4135 is resistant to external magnetic fields. the limitation on the ADUM4135 magnetic field immunity is set by the condition in which induced voltage in the transformer receiving coil is sufficie ntly large to either falsely set or reset the decoder. the following analysis defines the conditions under which a false reading condition can occur. the 2.3 v operating condition of the adum4 135 is examined because it represents the most susceptible mode of operation. 100 10 1 0.1 0.01 0.001 1k 10k 100k 1m 10m 100m maximum allowable magnetic flux density (kgauss) magnetic field frequency (hz) 13082-029 figure 25 . maximum allowable external magnetic flux density 1k 100 10 1 0.1 0.01 1k 10k 100k 1m 10m 100m maximum allowable current (ka) magnetic field frequency (hz) 13082-030 distance = 1m distance = 100mm distance = 5mm figure 26 . maximum allowable current for various current - to - ADUM4135 spacings insulation lifetime all insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. the rate of insulation degradation is depe ndent on the characteristics of the voltage waveform applied across the insulation , as well as on the materials and material interfaces. two types of insulation degradation are of primary interest: breakdown along surfaces exposed to air and insulation wea r out. surface breakdown is the phenomenon of surface tracking and the primary determinant of surface creepage requirements in system level standards. insulation wear out is the phenomenon where charge injection or displacement currents inside the insulati on material cause long - term insulation degradation. surface tracking surface tracking is addressed in electrical safety standards by setting a minimum surface creepage based on the working voltage, the environmental conditions, and the properties of the i nsulation material. safety agencies perform characterization testing on the surface insulation of components that allows the components to be categorized in different material groups. lower material group ratings are more resistant to surface tracking and therefore can provide adequate lifetime with smaller creepage. the minimum creepage for a given working voltage and material group is in each system level standard and is based on the total rms voltage across the isolation, pollution degree, and material g roup. the material group and creepage for the ADUM4135 isolator are presented in table 8 . insulation wear out the lifetime of insulation caused by wear out is determined by its thickness, material properties, and the voltage stress applied. it is important to verify that the prod uct lifetime is adequate at the application working voltage. the working voltage supported by an isolator for wear out may not be the same as the working voltage supported for tracking. it is the working voltage applicable to tracking that is specified in most standards. testing and modeling have shown that the primary driver of long - term degradation is displacement current in the polyimide insulation causing incremental damage. the stress on the insulation can be broken down into broad categories, such as: dc stress, which causes very little wear out because there is no displacement current, and an ac component time varying voltage stress, which causes wear out. the ratings in certification documents are usually based on 60 hz sinusoidal stress because thi s stress reflects isolation from line voltage. however, many practical applications have combinations of 60 hz ac and dc across the barrier as shown in equation 1. because only the ac portion of the stress causes wear out, the equation can be rearranged to solve for the ac rms voltage, as shown in equation 2. for insulation wear out with the polyimide materials used in this product, the ac rms voltage determines the product lifetime. 2 2 dc rms ac rms v v v + = ? = is t he total rms working voltage. v ac rms is the time varying portion of the working voltage. v dc is the dc offset of the working voltage.
ADUM4135 data sheet rev. a | page 16 of 17 calculation and use of parameters example the following is an example that frequently arises in power conversion appli cations. assume that the line voltage on one side of the isolation is 240 v ac rms , and a 400 v dc bus voltage is present on the other side of the isolation barrier. the isolator material is polyimide. to establish the critical voltages in determining the creepage clearance and lifetime of a device, see figure 27 and the following equations. isolation voltage time v ac rms v rms v dc v peak 13082-031 figure 27 . critical voltage example the working voltage across the barrier from equation 1 is 2 2 dc rms ac rms v v v + = + = rms v v rms = 466 v rms this working voltage of 466 v rms is used together with the material group and pollution degree when looking up the creepage required by a system standard. to determine if the lifetime is adequate, obtain the time varying portion of the working voltage. the ac rms voltage can be obtained from equation 2. 2 2 dc rms rms ac v v v ? = ? = rms ac v v ac rms = 240 v rms in this case, ac rms voltage is simply the line voltage of 240 v rms. this c alculation is more relevant when the waveform is not sinusoidal. the value of the ac waveform is compared to the limits for working voltage in table 8 for expected lifetime, less than a 60 hz sin e wave, and it is well within the limit for a 20 year service life. note that the dc working voltage limit in tabl e 8 is set by the creepage of the package as specified in iec 60664 - 1. this value may differ for specific system level standards. typical a pplicati on the typical application schematic in figure 28 shows a bipolar setup with an additional r blank resistor to increase charging current of the blanking capacitor for desaturation detection. the r blank resistor is optional. if unipolar operation is desired, the v ss2 supply can be removed, and v ss2 must be tied to gnd 2 . v ss1 ready fault reset v dd1 v dd1 r blank r g_on i c r g_off c blank r desat v ss2 v ss1 v i + v i ? 1 4 5 6 7 8 2 3 16 13 12 11 10 9 15 14 v ss2 v dd2 gnd 2 desat v ss2 gate_sense v out_on v out_off notes 1. grounds on primary and secondary side are isolated from each other. ADUM4135 1 2 2 1 1 v dd2 v rdesat v ce v f + + ? + ? ? 13082-032 figure 28 . typical application schematic
data sheet ADUM4135 rev. a | page 17 of 17 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-013-aa 10.50 (0.4134) 10.10 (0.3976) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0.75 (0.0295) 0.25 (0.0098) 45 1.27 (0.0500) 0.40 (0.0157) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 16 9 8 1 1.27 (0.0500) bsc 03-27-2007-b figure 29 . 16- lead standard small outline package [soic_w] wide body (rw - 16) dimensions shown in millimeters and (inches) ordering guide model 1 temperature range package description package option ADUM4135brwz ?40c to +125c 16- lead standard small outline package [soic_w] rw -16 ADUM4135brwz- rl ?40c to +125c 16- lead standard small outline package [soic_w], 13 tape and r eel rw -16 eval - ADUM4135ebz e valuation board 1 z = rohs compliant part. ? 2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d13082 -0- 9/15(a)

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